Chapter 10WBCHSE BoardClass XIIPhysics
Semiconductor Electronics
অর্ধপরিবাহী ও ডিজিটাল ইলেকট্রনিক্স
Energy bands in solids, intrinsic and extrinsic semiconductors, p-n junction diode formation, forward and reverse bias characteristics, half-wave and full-wave rectifiers, and fundamental digital logic gates.
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Syllabus Reference Module
Target Learning Objectives
- Distinguish conductors, semiconductors, and insulators using energy band gaps.
- Explain conduction in p-type and n-type semiconductors with majority and minority carriers.
- Analyze the V-I characteristics of p-n junction diodes under forward and reverse bias.
- Design half-wave and full-wave rectifier circuits and evaluate ripple factor.
- Formulate truth tables and Boolean operations for basic and universal logic gates (AND, OR, NOT, NAND, NOR).
Governing Physical Concepts
- Energy Band Gap (Eg) & Carrier Concentrations
- p-n Junction Depletion Layer & Barrier Potential
- Diode Forward & Reverse Bias V-I Curve
- Full-Wave Rectifier Circuit with Center-Tapped Transformer
- Logic Gates: NOT, OR, AND, NAND, NOR Truth Tables
Structured Concept Hierarchy
Chapter Topics & Breakdown
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Academic Library
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Quick Revision Summary
“NAND and NOR are universal gates capable of synthesizing any Boolean logic function.”
- •In intrinsic semiconductors, ne = nh = ni. In doped semiconductors, ne × nh = ni^2.
- •Barrier potential decreases under forward bias and increases under reverse bias.
- •Full-wave rectifier output ripple frequency is 2f (twice the input AC frequency).
Structured Practice Roadmap
Circuit analysis with ideal diodes, rectifier waveforms, and Boolean logic algebra.
Problem Bank Volume:20 Selected Problems
Problem Categories:
Diode Circuit AnalysisRectifier FrequencyLogic Gate Truth Tables
Board Diagnostic 10: Semiconductor Devices
Assessment Architecture • Academic Evaluation SpecificationBoard examination standard paper testing semiconductors and logic gates.
FormatWritten Board Paper
Duration45 Minutes
Coverage16 Questions
* Note: Written assessments are administered and reviewed directly by faculty. Digital diagnostic assessment engines are scheduled for subsequent platform phases.